1. Field of the Invention
This invention relates to design of memory circuits and particularly to an enhancement for DDR2 memory.
2. Description of the Related Art
One advantage of DDR2 memory structures is the ability to use clock speeds that are higher than typically found in DDR SDRAM (double-data-rate synchronous dynamic random access memory).
DDR SDRAM achieves greater bandwidth than ordinary SDR SDRAM (single-data-rate) by transferring data on both the rising and falling edges of the clock signal, and is considered “double pumped.” This effectively nearly doubles the transfer rate without increasing the frequency of the front side bus. Thus a 100 MHz DDR system has an effective clock rate of 200 MHz when compared to equivalent SDR SDRAM.
DDR2 is the new generation of DDR technology. The primary benefit is the potential for faster throughput. In addition, the DDR2 improves the power consumption of the DIMM because it works on a lower voltage. DDR operates at a range of 2.5 to 2.8 V, whereas DDR2 only requires 1.8 V. DDR2 consumes less power than DDR and offers a higher range of throughput because it has halved the speed of the memory core (thereby reducing power consumption), but offsetting that by doubling the number of prefetches from the memory core to the I/O buffers (from 2 to 4).
Both DDR and DDR2 are double pumped. That is, data is transferred on both the rising and the falling edges of the clock signal, or at points of 0.0 V and 2.5 V (1.8 V for DDR2). This achieves an effective data transfer rate of 200 MHz (and a theoretical bandwidth of 1.6 GB/s) with the same clock frequency when compared with SDR SDRAM operating at 100 MHz. The clock frequency for DDR2 is further boosted by electrical interface improvements, on-die termination, pre-fetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. The DDR2 pre-fetch buffer is 4 bits wide, whereas the pre-fetch buffer is 2 bits wide for DDR and 8 bits wide for DDR3.
In DDR2, power savings are achieved primarily due to an improved manufacturing process, resulting in a drop in of the operating voltage from 2.5 V for DDR to 1.8 V for DDR2. Further, DDR2 uses a real clock frequency of about half that of SDRAM while maintaining about the same bandwidth. The lower frequency at the memory core means less power consumption and the ability to increase data density (and therefore capacity), and increase speeds as manufacturing technology improves.
For DDR2 memory, improving wiring density and logic density present significant opportunities for performance enhancements. A need exists to increase logic functions while using a minimum circuit area to optimize the operation and use of DDR2 memory.